1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device which can provide required data flexibly under simplified control. The present invention has particular applicability to video random access memories (VRAMs).
2. Description of the Background Art
With recent use of semiconductor memories in various electronic equipment, various functions have become necessary. More specifically, although a semiconductor memory basically has a function of storing applied (or predetermined) data and reading the stored data, an additional function of access has become necessary. In particular, to carry out video signal processing or image signal processing at a high speed, serial access, that is, serial reading and/or serial writing of data signals, has become necessary.
As a random access memory (RAM) having a serial access function, a video RAM and a field memory, for example, are known. The video RAM has a random access port and a serial access port. An applied data signal is stored in an externally designated memory cell through the random access port, and the stored data signal is read out from the externally designated memory cell. On the other hand, the data signal applied through the serial access port is serially stored in an externally designated memory cell row, and the stored data signal is serially read out from the externally designated memory cell row. In order to carry out image signal processing at a high speed, the random access port is frequently used, while the serial access port is used for supplying processed, that is, stored pixel signals to an image indication device such as CRT at a high speed.
Although the present invention is generally applicable to a semiconductor memory having a serial access function, for simplicity of description, an example where the present invention is applied to the video RAM will be described hereinafter.
FIG. 13 is a block diagram of the video RAM showing the background of the present invention. Referring to FIG. 13, a video RAM 600 includes a memory cell array 1 provided with a multitude of memory cells (not shown) arranged in rows and columns, a row decoder 5 for selecting a memory cell row in response to an externally applied row address signal, a column decoder 6 for selecting a memory cell column in response to an externally applied column address signal, and a sense amplifier 2 for amplifying a data signal read out from the memory cell array 1. A row address buffer 4a applies row address signals included in externally applied address signals A0 to An to the row decoder 5. A column address buffer 4b applies column address signals included in address signals A0 to An to the column decoder 6.
A random access operation is carried out as in the following. In the reading operation, a data signal stored in a memory cell in a row selected by the row decoder 5 is amplified by the sense amplifier 2. The column decoder 6 selects one column through an IO gate circuit 3, and the amplified data signal of the selected column is applied to a preamplifier 7a. The data signal amplified by the preamplifier 7a is provided through a main amplifier 7b as output data DQ.
In the writing operation, the input data DQ is applied to a DIN buffer (data in buffer) 7c. A write circuit 7d amplifies an input data signal to apply the amplified signal to the memory cell array 1 through the IO gate circuit 3. The column decoder 6 selects one column through the IO gate circuit 3, and the row decoder 5 selects one memory cell row. Therefore, the input data signal is stored in the memory cell designated by the row decoder 5 and the column decoder 6.
The serial access operation is carried out as in the following. In the reading operation, the row decoder 5 selects one memory cell row, and the data signal stored in the memory cell in the selected row is amplified by the sense amplifier 2. Since a transfer gate circuit 11 is turned on in response to a transfer control signal .PHI.r generated from a timing control circuit 44, the data signal in one selected row is applied to a data register 12. A serial counter 13 sequentially selects data held in the data register 12 in response to an output signal from a serial counter 100. Therefore, the stored data signal is provided as serial output data SQ after amplification by a preamplifier 14a and a main amplifier 14b.
The timing control circuit 44 receives various externally applied control signals /RAS, /CAS, /DT, /OE, /WB, /WE and /SE and a serial clock signal SC. The signal/RAS corresponds to a row address strobe signal. The signal/CAS corresponds to a column address strobe signal. The timing control circuit 44 provides a clock signal .PHI.sc for driving the serial counter 100 in response to the serial clock signal SC. In addition to this, the timing control circuit 44 provides the transfer control signal .PHI.r in response to the signal /RAS serving as a state control signal.
FIG. 14 is a timing chart for explaining the serial reading operation of the video RAM shown in FIG. 13. Referring to FIG. 14, since the signal /RAS falls when the signal /DT is at a low level, a transfer cycle TC1 is initiated.
The externally applied address signals A0 to An include a row address signal denoting a row R1 and column address signal denoting a column I. When the transfer cycle TC1 is initiated, the row address signal R1 is stored in the row address buffer 4a. The row decoder 5 selects one row in the memory cell array 1 by decoding the stored row address signal R1. The data signal stored in the memory cell of the selected row is amplified by the sense amplifier 2.
After the signal /CAS falls, the column address signal I is stored in the column address buffer 4b. Since the transfer gate circuit 11 is turned on in response to the transfer control signal .PHI.r after the rise of the signal /DT, the data signal amplified by the sense amplifier 2 is transferred to the data register 12 to be stored therein. Simultaneously, the column address signal I stored in the column address buffer 4b is applied to the serial counter 100 as an initial value. The serial counter 100 starts counting to apply an output signal to the serial selector 13 in response to the clock signal .PHI.sc applied from the timing control circuit 44.
The serial selector 13 sequentially selects data from one row of data signals stored in the data register 12 starting from the data designated by the column address signal I. The selected data is sequentially provided as the serial output data SQ after amplification by the preamplifier 14a and the main amplifier 14b. The result is that, in response to the serial clock signal SC, the Ith data and et seq. of the data stored in the selected row R1 of the memory cell array 1 are provided as the serial output data SQ.
Similarly, operations in the next transfer cycle TC2 are also continued. In the transfer cycle TC2, data stored in a row R2 of the memory cell array 1 is transferred to the data register 12, and the Jth data and et seq. are serially read out.
In a period between the transfer cycles TC1 and TC2, the serial data output is carried out as described before, while an asynchronous random access operation can be carried out independently of the serial reading operation. In other words, since the transfer gate circuit 11 is off in this period, random access can be carried out through a random access port DQ.
FIG. 15 is a memory matrix diagram for explaining a concept of oblique reading in the video RAM. The memory matrix shown in FIG. 15 corresponds to part of one screen in the image indication. In other words, each element constituting the memory matrix corresponds to each of pixel signals p0 to p7, p10 to p17, . . . and the like constituting one screen.
In access to the video RAM, the "oblique reading" shown in FIG. 15 is sometimes required. In the oblique reading, after, eight pixel data p0 to p7 stored in the row R1 in the memory cell array, for example, are read out, eight pixel signals p10 to p17 stored in the next row R2 are read out. Since the similar reading is also required in other rows, the oblique reading is carried out. The oblique reading as shown in FIG. 15 is utilized in, for example, the following image processing.
FIG. 16(a) shows a memory matrix storing pixel signals for indicating image "A". Data stored in the memory matrix is sequentially read out along each row, whereby the image shown in FIG. 16(b) can be obtained by the read data. Therefore, FIGS. 16(a) and (b) show an example of ordinary horizontal reading.
In the oblique reading, as shown in FIG. 16(c), data stored in the memory matrix is sequentially read out in the oblique direction. The image shown in FIG. 16(d) can be obtained by using the read data. As can be seen from comparison between FIGS. 16(b) and (d), a rotated image can be obtained by carrying out the oblique reading. More specifically, the oblique reading is useful for rotation processing in image processing, as one example. The oblique reading shown in FIG. 16(c) can be implemented as shown in, for example, FIG. 15.
As described above, although the oblique reading is useful in image processing, there is a problem that timing control of externally applied control signals is difficult. In other words, referring to FIG. 14, when the row R1 where the serial reading is carried out is changed to the next new row R2, synchronization of the control signal /DT and the serial clock signal SC is required, and the synchronization control is difficult. It is pointed out that timing control is particularly difficult in image processing where high speed processing is required.
FIG. 17 is a block diagram of another video RAM showing the background of the present invention. A video RAM 700 shown in FIG. 17 has a "split function". Description on the "split function" is given in, for example, the U.S. Pat. No. 4,855,959. A semiconductor memory having the split function is provided with a data register holding upper bit data and a data register holding lower bit data of data stored in one row of a memory cell array. Transfer of data is carried out from the memory cell array to one of the two data registers, while the serial data is provided from the other of the data registers. Transfer and serial output of data from the two data registers are carried out alternately.
Referring to FIG. 17, the video RAM 700 includes divided transfer gate circuits 11a, 11b, divided data registers 12a, 12b, and divided serial selectors 13a, 13b for implementing the split function. The address buffer 4 includes a row address buffer and a column address buffer. The transfer gate circuits 11a and 11b operate in response to a control signal applied from the transfer control circuit 10.
A serial selector control circuit 53 for controlling the serial selectors 13a and 13b includes an address pointer 16, a serial counter 17, switching circuits 31 and 32, and a finally determining circuit 40. A timing control circuit 45 provides control signals DSF, ATWL, SPWL and SPL for controlling various operations in the video RAM 700.
FIG. 18 is a timing chart for explaining operations in the transfer cycle of the video RAM shown in FIG. 17. Referring to FIGS. 17 and 18, operations in the transfer cycle will now be described. After the signal /DT falls, in response to the fall of the signal /RAS, the transfer cycle is initiated, whereby input/output through the random access port is inhibited. After the data signal stored in the row selected by the row decoder 5 is amplified by the sense amplifier 2, the transfer gate circuits 11a and 11b are turned on in response to the rise of the signal /DT. Therefore, data of one row is applied to the data registers 12a and 12b to be stored therein. On the other hand, a column address signal I indicating an initial address in the serial reading is externally applied through the address buffer 4. The column address signal I is applied to the address pointer 16 through the switching circuit 31, and transferred to the serial counter 17 through the switching circuit 32.
The serial counter 17 initiates a counting operation from an initial address I in response to a clock signal SC applied from the timing control circuit 45. The serial selectors 13a and 13b sequentially select data held in the data registers 12a and 12b starting from the Ith data in response to an output signal from the serial counter 17. Therefore, the Ith data and et seq. of the data in the row R1 are sequentially provided as serial output data SQ. It is pointed out that reading and writing of data through the random access port can be implemented asynchronously while the serial output of the data is carried out.
FIG. 19 is a timing chart for explaining operations of the split function of the video RAM shown in FIG. 17. Referring to FIG. 19, initial transfer is carried out by using a normal transfer mode in a period T30. Therefore, data of the row R1 selected by the row decoder 5 is transferred to the data registers 12a and 12b through the transfer gate circuits 11a and 11b. In addition to this, the column address signal I indicative of the initial address is also applied to the serial counter 17 in response to the pulse signals ATWL and SPWL.
The split transfer is carried out in a period T31. In this period, since the serial counter 17 provides a low level signal QSF, the latter half of the data stored in a row selected by the row decoder 5 is transferred to the data register 12b through the transfer gate circuit 11b. On the other hand, in this period, the Ith data and et seq. of the data held in the data register 12a are provided outside as the serial output data SQ in response to the serial clock signal SC. In this period T31, furthermore, the row address signal R1 and a column address signal J for the split transfer in the next period T32 are applied to the address buffer 4. The column address signal J is used as the initial address in the next split transfer period T32. In response to the pulse signal ATWL, and stored therein the column address signal J is applied to the address pointer 16 through the switching circuit 31, and stored therein.
In the period T32, the next split transfer is carried out. In this period T32, since a high level signal QSF is provided from the serial counter 17, the former half of the data of the row R1 designated in the previous period T31 is applied to the data register 12a through the transfer gate circuit 11a. The Jth data and et seq. of the data stored in the data register 12b are sequentially provided outside in response to the serial clock signal SC.
It is pointed out that random access through the random access port, that is, random reading and random writing, can be carried out in periods T41 and T42 shown in FIG. 19.
FIG. 11 is a concept diagram showing input/output of the data registers 12a and 12b in the split transfer shown in FIG. 19. Referring to FIG. 11, in the initial transfer period T30, the row address signal R1 and the column address signal I (not shown) for the split transfer in the next period T31 are applied. In the period T31, the Ith data and et seq. of the data stored in the data register 12a are provided through the serial input/output buffer 14. In this period T31, the data in the row R1 is transferred to the data register 12b.
In the next split transfer period T32, data of the row R2 is transferred to the data register 12a. In this period T32, the Jth data and et seq. of the data stored in the data register 12b are provided.
Furthermore, in a period T33, the Kth data and et seq. of the data stored in the data register 12a are provided, while data of the next new row is transferred to the data register 12b.
As can be seen from FIG. 11, although column addresses I, J, K, . . . , and the like of the first data to be provided of the data stored in the data registers 12a and 12b are externally designated, the last address to be provided of each of the registers 12a and 12b can not be externally designated. Therefore, for example, in the period T31, all of the Ith data and et seq. of the data stored in the data register 12a are read out regardless of necessity.
Referring to FIG. 20, it is assumed that pixel data for indicating areas AR1 and AR2 in the screen SCR is required. For facility of understanding, the screen SCR can be considered to correspond to a memory cell array in the video RAM. In such a case, the video RAM 700 shown in FIG. 17 provides the pixel data shown in FIG. 21 since it carries out the split transfer shown in FIG. 11.
Referring to FIG. 21, the video RAM 700 provides pixel data for indicating areas AR3 and AR4 on the screen SCR. In other words, since the video RAM 700 provides data which is not actually required, the operation time is consumed for unnecessary access.
As described above, the video RAM 600 shown in FIG. 13 requires synchronization of the signal /DT and the serial clock signal SC in order to carry out the oblique reading, thereby suffering from a difficulty in synchronous control under requirement of a high speed operation.
In addition to this, as can be seen from comparison of FIGS. 20 and 21, the video RAM 700 shown in FIG. 17 consumes access time for providing unnecessary data, thereby posing a problem that the high speed operation in image processing is hampered.